1. Field of the Invention
The present invention relates to a charging pump circuit and a phase-locked loop circuit using the charging pump circuit, and more particularly to a charging pump circuit which is so constructed that the phase-locked loop circuit using the same may be affected by little or no jitter.
2. Prior Art
A phase-locked loop circuit (hereinafter acronym "PLL" will be used) is well known. Referring to FIG. 5, it comprises a phase comparator 63, a charging pump circuit 64 connected to the phase comparator 63, a loop filter 65 connected to the charging pump circuit 64, a voltage controlled oscillator (hereinafter acronym "VCO" will be used) 61 connected to the loop filter 65, and a frequency divider 62 whose input and output terminals are connected to the VCO 61 and to the phase comparator 63 respectively, thus making up a loop circuit. The phase comparator 63 is responsive to an exterior signal IN and a division of the oscillating signal from the VCO 61 for making a phase-comparison between them and providing a phase-leading signal U at its first output terminal and a phase-lagging signal D at its second output terminal. The charging pump circuit 64 is responsive to the signal U or D from the phase comparator 63 for providing a signal representing the phase difference when detected, and the loop filter 65 is responsive to the signal from the charging pump circuit for providing a control signal for the VCO 61. More specifically, in operation the oscillating signal from the VCO 61 is divided by the frequency divider 62 so that the frequency of the oscillating signal thus divided may be equal to the frequency of the exterior signal IN, and then the frequency-divided signal is supplied to the phase comparator 63, where a phase-comparison is made between the exterior signal IN and the frequency-divided signal.
In case that the exterior signal IN (standard) leads ahead of the oscillating signal in phase, the phase-comparator 63 provides a phase-leading signal U at its first output terminal. On the contrary, in case that the exterior signal IN (standard) lags behind the oscillating signal in phase, and then, the phase-comparator provides a phase-lagging signal D at its second output terminal.
The charging pump circuit 64 is driven by the phase-leading signal U and phase-lagging signal D from the phase-comparator 63 and produces a signal representing the phase difference and supplies it to the loop filter 65, where high-frequency components including noise signals are eliminated to provide a control voltage for the VCO 61. The PLL circuit will be locked when the oscillating output signal OUT is brought in phase-synchronism with the exterior signal IN.
Referring to FIG. 6A, one example of charging pump circuit 64 comprises a PMOS transistor 21 having an inverter 23 connected to its gate electrode and an NMOS transistor 22 connected in series to the PMOS transistor 21. Application of a phase-leading signal U to the PMOS transistor 21 via the inverter 28 will cause the transistor 21 to be turned on or off, whereas application of a phase-lagging signal D to the NMOS transistor 22 will cause the transistor 22 to be turned on or off.
FIG. 6B shows signal waveforms appearing at different points of the charging pump circuit 64. Usually a capacitive load is connected to the output terminal Y of the charging pump circuit 64. Application of a phase-leading signal U (HIGH) to the PMOS transistor 21 will cause an electric current i to flow through the transistor 21 now turned on, thereby charging the capacitive load with electricity. Accordingly the voltage rises at the output terminal Y. On the contrary, application of a phase-lagging signal D (HIGH) to the NMOS transistor 22 will allow an electric current i to flow through the transistor 22 now turned on to discharge the capacitive load. Accordingly the voltage descends at the output terminal Y.
FIG. 6B shows how the charging or discharging current i varies, and how the voltage at the output terminal Y varies. As seen from the drawing, the length of time taken for potential leveling and the change in output voltage increases with the duration of the phase-leading or phase-lagging pulse signal U or D. This is a major cause of the increase of jitter, which causes a side effect on a PLL circuit using such charging pump circuit.